The present disclosure generally relates to the field of electronics. More particularly, an embodiment of the invention relates to techniques to improve input/output (I/O) performance in multiple core processors.
How I/O data is made available to a processor may be a key factor in data processing performance. For example, some I/O adapters may take advantage of direct memory access (DMA) techniques to write I/O data into system memory concurrent to processor execution. Hence, DMA mechanisms may decouple processors from the burden of moving data from an I/O source into system memory. However, in situations where a processor needs to manipulate I/O data, processor to memory accesses may still become a significant source of inefficiency.
Moreover, some processors may include a private level 1 (L1) cache that may cache data locally for faster access. For example, direct cache access (DCA) may be used to transfer data from an I/O device into a processor's L1 cache. Accordingly, DCA may be used to reduce system memory access latency. However, placing I/O data into a processor's L1 cache may consume valuable space in the processor's L1 cache.